1. Field of the Invention
The present invention relates to a semiconductor storage device and, more particularly, to an internal clock signal generating circuit in a clock-synchronized semiconductor storage device.
2. Description of the Prior Art
In recent years, there have been developed various clock-synchronized semiconductor storage devices comprising an internal clock signal generator for generating a clock signal corresponding to an external spec in a chip for an external clock signal extclk with an increase in a frequency. Typical examples of the internal clock signal generator include a PLL (Phase-Locked-Loop), DLL (Delay-Locked-Loop) and the like, which are generally used for clock-synchronized semiconductor devices other than the semiconductor storage device. These circuits include a phase comparing circuit for deciding whether the phase of the external clock signal extclk is coincident with that of an internal clock signal intclk.
FIG. 12 is a schematic block diagram showing an example of an internal clock signal generator in a conventional clock-synchronized semiconductor storage device.
In FIG. 12, an internal clock signal generator 100 comprises a phase variable circuit 101 and a phase comparing circuit 102. The result of comparison of the phase of the external clock signal extclk with that of the internal clock signal intclk which is obtained by the phase comparing circuit 102 is instantaneously fed back to the phase variable circuit 101.
FIG. 13 is a diagram showing an example of the phase variable circuit 101. Switches are provided between each of outputs of a plurality of buffer circuits connected forward in series and that of the phase variable circuit 101, respectively. One of the switches is turned on and closed in response to the result of the comparison obtained by the phase comparing circuit 102, and a clock signal output from the output terminal of the buffer circuit corresponding to the switch is output as the internal clock signal intclk from the output terminal of the phase variable circuit 101.
The phase variable circuit 101 turns one of the switches shown in FIG. 13 on in response to the result of the comparison obtained by the phase comparing circuit 102, and outputs, as the internal clock signal intclk, a clock signal generated by changing the phase of the input external clock signal extclk. For example, the phase variable circuit 101 generates the internal clock signal intclk having a phase delayed by one cycle for the external clock signal extclk. In this case, the phase variable circuit 101 generates the internal clock signal intclk by adjustment such that the phase of the internal clock signal intclk delayed by one cycle is matched with that of the external clock signal extclk according to the result of the comparison of the phase comparing circuit 102.
However, the method of instantaneously feeding the result of the comparison, obtained by the phase comparing circuit 102, back to the phase variable circuit 101 has the following drawbacks. More specifically, the phase comparing resolution of the phase comparing circuit 102 is reduced due to a fluctuation in a source voltage or the like, and a feedback system including the buffer circuit 103 and the phase comparing circuit 102 malfunctions to cause an oscillation when the error of the result of the comparison is shifted by the minimum step of the phase variable circuit 101 or more through the malfunction of the phase comparing circuit 102, that is, at least one of the positions of the switch to be turned on shown in FIG. 13 is shifted.
Japanese Patent Laid-Open Publication No. 63-161568 discloses a digital phase control circuit for use with a floppy disk drive device, in which the phase difference between input data and an output signal is detected, N values held in N registers are averaged and a phase is shifted according to the average value.
In order to eliminate the above-mentioned drawbacks, it is an object of the present invention to provide a stable internal clock signal generator capable of preventing an oscillation from being generated through a fluctuation in a power source or the like by averaging a predetermined number of comparison results in a phase comparing circuit and outputting the average value as a comparison result to a phase variable circuit.
In order to achieve the above-mentioned object, the present invention provides an internal clock signal generator for generating and outputting an internal clock signal constituting a clock signal, which may be used as a clock signal for every circuit component of a semiconductor storage device from an external clock signal inputted from an outside. This internal clock signal generator includes a phase comparing section for comparing phases of the external clock signal and the generated internal clock signal every predetermined cycle and outputting a binary comparison result indicating whether the phase of the internal clock signal is advanced or delayed for that of the external clock signal, a comparison result storing section for sequentially storing the binary comparison result compared by the phase comparing section and for storing a predetermined number of comparison results, a phase deciding section for deciding more comparison results as a phase state of the internal clock signal for the external clock signal in relation to each comparison result stored in the comparison result storing section, and a phase variable section for adjusting the phase of the generated internal clock signal and outputting the adjusted signal according to a result of the decision obtained by the phase deciding section every time the predetermined number of comparison results are stored in the comparison result storing section.
According to the above-mentioned structure, the phase state of the internal clock signal is decided by using the phase comparison results obtained by the comparison carried out a predetermined number of past times. Therefore, it is possible to prevent the phase comparison resolution from being reduced due to a fluctuation in a power source or the like and an oscillation from being caused by the erroneous phase comparison result.
Moreover, it is desirable that the phase deciding section should decrease the number of the comparison results to be used for deciding the phase state to decide the phase state of the internal clock signal when a phase difference between the external clock signal and the internal clock signal exceeds a predetermined value. With such structure of the phase deciding section, when the phase difference between the external clock signal and the internal clock signal is great, the speed of the phase adjustment can be increased and the internal clock signal can be stabilized in the early stage.
According to a preferred embodiment, the phase deciding section decreases the number of the comparison results to be used for deciding the phase state to decide the phase state of the internal clock signal for a predetermined period in which the phase difference between the external clock signal and the internal clock signal exceeds the predetermined value. With such a structure, it is possible to detect the state in which the phase difference between the external clock signal and the internal clock signal is great without deciding whether the phase difference between the external clock signal and the internal clock signal is increased.
According to another embodiment, the phase deciding section decreases the number of the comparison results to be used for deciding the phase state to decide the phase state of the internal clock signal for a predetermined time after a power source is turned on. Consequently, it is possible to easily detect the state in which the phase difference between the external clock signal and the internal clock signal is great without deciding whether the phase difference between the external clock signal and the internal clock signal is increased.
Moreover, it is desirable that the phase deciding section should decrease the number of the comparison results to be used for deciding the phase state to decide the phase state of the internal clock signal for a predetermined time after a return from a low consumed current operation mode to a normal operation mode in the semiconductor storage device. Consequently, it is possible to easily detect the state in which the phase difference between the external clock signal and the internal clock signal is great without deciding whether the phase difference between the external clock signal and the internal clock signal is increased.
Furthermore, the phase deciding section may decrease the number of the comparison results to be used for deciding the phase state to decide the phase state of the internal clock signal when a difference between one of comparison result numbers and the other comparison result number exceeds a predetermined number for each of the comparison results stored in the comparison result storing section. With such structure, when the phase difference between the external clock signal and the internal clock signal is great, the speed of the phase adjustment can be increased without detecting, in other circuits, a period in which the phase difference between the external clock signal and the internal clock signal is great. Thus, the internal clock signal can be stabilized in the early stage. Furthermore, the unexpected unstable state of the internal clock signal can be detected on the inside and the internal clock signal can be stabilized more quickly.